TY - JOUR
T1 - A memory efficient realization of cyclic convolution and its application to discrete cosine transform
AU - Chen, Hun Chen
AU - Guo, Jiun-In
AU - Jen, Chein Wei
PY - 2003/7/14
Y1 - 2003/7/14
N2 - This paper presents a memory efficient design for realizing the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic computation, and exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel and then separate the kernel to be two perfect cyclic forms to facilitate an efficient realization of 1-D N-point DCT using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and N-1/2+1 accumulators. The comparison results with the existing designs show that the proposed design can reduce delay-area product significantly.
AB - This paper presents a memory efficient design for realizing the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic computation, and exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel and then separate the kernel to be two perfect cyclic forms to facilitate an efficient realization of 1-D N-point DCT using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and N-1/2+1 accumulators. The comparison results with the existing designs show that the proposed design can reduce delay-area product significantly.
UR - http://www.scopus.com/inward/record.url?scp=18144448950&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2003.1205766
DO - 10.1109/ISCAS.2003.1205766
M3 - Conference article
AN - SCOPUS:18144448950
SN - 0271-4310
VL - 4
SP - 33
EP - 36
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
Y2 - 25 May 2003 through 28 May 2003
ER -