A maskable memory architecture for rank-order filtering

Meng Chun Lin*, Lan-Rong Dung

*此作品的通信作者

研究成果: Paper同行評審

摘要

This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a bit-serial rank-order filtering algorithm the proposed design uses a special-defined memory,' called parallel maskable memory (PMM) to realize major operations of rank-order filtering, polarization and update. Using the memory-orient architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined datapath. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits. The bit-sliced read with a polarization selector allows PMM to perform polar determination while the partial write helps next-bit update. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed.

原文English
頁面453-456
頁數4
DOIs
出版狀態Published - 6 12月 2004
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 6 12月 20049 12月 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區Taiwan
城市Tainan
期間6/12/049/12/04

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