A low-voltage low-distortion MOS sampling switch

Chun Yueh Yang, Chung-Chih Hung

研究成果: Conference article同行評審

18 引文 斯高帕斯(Scopus)

摘要

In order to reduce distortion due to variation of the gate overdrive and the threshold voltage, a novel low-voltage constantresistance sampling switch is proposed in this paper. The technique to reduce nonlinearity can be used in a high resolution sample and hold circuit. TSMC 0.18um standard CMOS technology is utilized in this research. Results indicate that much lower Total Harmonic Distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of the low-voltage low-distortion switched-capacitor circuits.

原文English
文章編號1465291
頁(從 - 到)3131-3134
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 23 5月 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 5月 200526 5月 2005

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