A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS

Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

A low voltage buck DC-DC converter (0.45-V input, 0.4-V output) with on-chip gate boosted (OGB) and clock frequency scaled digital PWM controller is designed in 40-nm CMOS process. The highest efficiency to date is achieved at the output power less than 40μW. In order to compensate for the die-to-die delay variations of a delay line in the proposed digital PWM controller, a linear delay trimming by a logarithmic stress voltage (LSV) scheme with good controllability is also proposed and verified in measurement.

原文English
主出版物標題2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
頁面109-110
頁數2
DOIs
出版狀態Published - 20 5月 2013
事件2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
持續時間: 22 1月 201325 1月 2013

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
國家/地區Japan
城市Yokohama
期間22/01/1325/01/13

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