Supply noise caused by fluctuation of peak current is increasingly important for SoC. This work proposes a content-sensitive architecture to effectively reduce the fluctuation of peak current and lower power consumption of ROMs for various code-patterns and cycles. We achieve both by arranging the data patterns of ROM and by adjusting the bitline structures accordingly. Our experiments on 0.25μm 256K bits ROM macros have shown that the fluctuation of peak current and power consumptions are less than 1.02% of the value using conventional approaches.
|出版狀態||Published - 12月 2004|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 6 12月 2004 → 9 12月 2004
|Conference||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||6/12/04 → 9/12/04|