A low-power viterbi decoder based on scarce state transition and variable truncation length

Dah Jia Lin; Chien Ching Lin; Chih Lung Chen; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/VDAT.2007.373220

A low-power viterbi decoder based on scarce state transition and variable truncation length

Dah Jia Lin^*, Chien Ching Lin, Chih Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

6 引文斯高帕斯（Scopus）

摘要

The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.

原文	English
主出版物標題	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VDAT.2007.373220
出版狀態	Published - 28 9月 2007
事件	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan 持續時間: 25 4月 2007 → 27 4月 2007

出版系列

名字	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
國家/地區	Taiwan
城市	Hsinchu
期間	25/04/07 → 27/04/07

存取文件

10.1109/VDAT.2007.373220

其它文件與鏈接

Link to publication in Scopus

引用此

Lin, D. J., Lin, C. C., Chen, C. L., Chang, H-C., & Lee, C-Y. (2007). A low-power viterbi decoder based on scarce state transition and variable truncation length. 於 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers 文章 4239412 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373220

Lin, Dah Jia ; Lin, Chien Ching ; Chen, Chih Lung 等. / A low-power viterbi decoder based on scarce state transition and variable truncation length. 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

@inproceedings{9205748f400f483083982565ebed5b14,

title = "A low-power viterbi decoder based on scarce state transition and variable truncation length",

abstract = "The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.",

author = "Lin, {Dah Jia} and Lin, {Chien Ching} and Chen, {Chih Lung} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2007",

month = sep,

day = "28",

doi = "10.1109/VDAT.2007.373220",

language = "English",

isbn = "1424405831",

series = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

booktitle = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

note = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 ; Conference date: 25-04-2007 Through 27-04-2007",

}

Lin, DJ, Lin, CC, Chen, CL, Chang, H-C & Lee, C-Y 2007, A low-power viterbi decoder based on scarce state transition and variable truncation length. 於 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers., 4239412, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, Hsinchu, Taiwan, 25/04/07. https://doi.org/10.1109/VDAT.2007.373220

A low-power viterbi decoder based on scarce state transition and variable truncation length. / Lin, Dah Jia; Lin, Chien Ching; Chen, Chih Lung 等.
2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239412 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A low-power viterbi decoder based on scarce state transition and variable truncation length

AU - Lin, Dah Jia

AU - Lin, Chien Ching

AU - Chen, Chih Lung

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

PY - 2007/9/28

Y1 - 2007/9/28

N2 - The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.

AB - The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.

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U2 - 10.1109/VDAT.2007.373220

DO - 10.1109/VDAT.2007.373220

M3 - Conference contribution

AN - SCOPUS:34648819535

SN - 1424405831

SN - 9781424405831

T3 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

BT - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

T2 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007

Y2 - 25 April 2007 through 27 April 2007

ER -

Lin DJ, Lin CC, Chen CL, Chang H-C , Lee C-Y. A low-power viterbi decoder based on scarce state transition and variable truncation length. 於 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239412. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2007.373220

A low-power viterbi decoder based on scarce state transition and variable truncation length

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Conference

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