TY - JOUR
T1 - A low-power synchronizer for multistandard wireless communications
AU - Tsai, Tsung Heng
AU - Chen, Yi Jen
AU - Li, Chi Fang
AU - Pu, Guo Hua
AU - Chu, Yuan Sun
N1 - Funding Information:
Manuscript received August 13, 2007; revised November 23, 2007, and January 4, 2008. Published August 13, 2008 (projected). This work was supported by the National Science Council of Taiwan under Grant NSC 95-2221-E-194-093-MY2. This paper was recommended by Associate Editor A. Tasic.
PY - 2008
Y1 - 2008
N2 - This paper proposes a low-power ASIC design of pseudonoise code synchronization for wireless code-division multiple access (WCDMA), CDMA2000, and IEEE 802.11 g systems. WCDMA and CDMA 2000 are two major standards in third-generation (3G) communication systems. Since 3G and 802.11 g are based on the same CDMA technology, there are common parts in the code synchronization hardware. We integrate the three systems on one ASIC. In addition, we use three kinds of low-power techniques in the design that include power management, absolute weighted magnitude calculation, and spurious power suppression adder. They can save 57.37% power consumption in WCDMA synchronization, 6.06% power consumption in CDMA2000 synchronization, and 84.69% power consumption in 802.11 g synchronization. The low-power synchronizer is implemented with an operating voltage of 1.2 V, 0.13-μm CMOS technology, and chip area of 2.1 × 2.1 mm2.
AB - This paper proposes a low-power ASIC design of pseudonoise code synchronization for wireless code-division multiple access (WCDMA), CDMA2000, and IEEE 802.11 g systems. WCDMA and CDMA 2000 are two major standards in third-generation (3G) communication systems. Since 3G and 802.11 g are based on the same CDMA technology, there are common parts in the code synchronization hardware. We integrate the three systems on one ASIC. In addition, we use three kinds of low-power techniques in the design that include power management, absolute weighted magnitude calculation, and spurious power suppression adder. They can save 57.37% power consumption in WCDMA synchronization, 6.06% power consumption in CDMA2000 synchronization, and 84.69% power consumption in 802.11 g synchronization. The low-power synchronizer is implemented with an operating voltage of 1.2 V, 0.13-μm CMOS technology, and chip area of 2.1 × 2.1 mm2.
KW - Code-division multiple access (CDMA)
KW - Synchronization
KW - Wireless communication systems
UR - http://www.scopus.com/inward/record.url?scp=50549096627&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2008.922352
DO - 10.1109/TCSII.2008.922352
M3 - Article
AN - SCOPUS:50549096627
SN - 1549-7747
VL - 55
SP - 826
EP - 830
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 8
ER -