TY - JOUR
T1 - A low-power smart vision system-on-a-chip design for ultra-fast machine vision applications
AU - Fang, Wai Chi
N1 - Publisher Copyright:
© 1998 SPIE. All rights reserved.
PY - 1998/3/25
Y1 - 1998/3/25
N2 - In this paper, an ultra-fast smart vision system-on-a-chip design is proposed to provide effective solutions for real time machine vision applications by taking advantages of recent advances in integrated sensing/processing designs, electronic neural networks, advanced microprocessors and sub-micron VLSI technology. The smart vision system mimics what is inherent in biological vision systems. It is programmable to perform vision processing in all levels such as image acquisition, image fusion, image analysis, and scene interpretation. A system-on-a-chip implementation of this smart vision system is shown to be feasible by integrating the whole system into a 3-cm × 3-cm chip design in a 0.18-μm CMOS technology. The system achieves one tera-operation-per-second computing power that is a two order-of-magnitude increase over the state-of-the-art microcomputer and DSP chips. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation. This highly integrated smart vision system can be used for various NASA scientific missions and other military, industrial or commercial vision applications.
AB - In this paper, an ultra-fast smart vision system-on-a-chip design is proposed to provide effective solutions for real time machine vision applications by taking advantages of recent advances in integrated sensing/processing designs, electronic neural networks, advanced microprocessors and sub-micron VLSI technology. The smart vision system mimics what is inherent in biological vision systems. It is programmable to perform vision processing in all levels such as image acquisition, image fusion, image analysis, and scene interpretation. A system-on-a-chip implementation of this smart vision system is shown to be feasible by integrating the whole system into a 3-cm × 3-cm chip design in a 0.18-μm CMOS technology. The system achieves one tera-operation-per-second computing power that is a two order-of-magnitude increase over the state-of-the-art microcomputer and DSP chips. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation. This highly integrated smart vision system can be used for various NASA scientific missions and other military, industrial or commercial vision applications.
KW - Active pixel sensor
KW - Neural processor
KW - Smart sensor
KW - System-on-a-chip
KW - Vision system
UR - http://www.scopus.com/inward/record.url?scp=85076960699&partnerID=8YFLogxK
U2 - 10.1117/12.304795
DO - 10.1117/12.304795
M3 - Conference article
AN - SCOPUS:85076960699
SN - 0277-786X
VL - 3390
SP - 666
EP - 675
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
T2 - Applications and Science of Computational Intelligence 1998
Y2 - 13 April 1998 through 17 April 1998
ER -