A low power reconfigurable SAR ADC for CMOS MEMS sensor

Hao Min Lin, Kuei-Ann Wen

    研究成果: Conference contribution同行評審

    4 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a reconfigurable successive approximation register (SAR) Analog-to-Digital Converter (ADC) of which the resolution can be scaled from 9 to 12 bits for various inertial MEMS sensor applications. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In addition, level shifter connects the interface between digital and analog domain. 3 bit segmented capacitor array are used to decrease the static error and glitches from MSB switching. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 μW and achieve 52.3, 57.7, 63.2 and 68.6 SNDR respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4fJ/conversion-step.

    原文English
    主出版物標題Proceedings - International SoC Design Conference 2017, ISOCC 2017
    發行者Institute of Electrical and Electronics Engineers Inc.
    頁面7-8
    頁數2
    ISBN(電子)9781538622858
    DOIs
    出版狀態Published - 29 5月 2018
    事件14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
    持續時間: 5 11月 20178 11月 2017

    出版系列

    名字Proceedings - International SoC Design Conference 2017, ISOCC 2017

    Conference

    Conference14th International SoC Design Conference, ISOCC 2017
    國家/地區Korea, Republic of
    城市Seoul
    期間5/11/178/11/17

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