With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. In the Viterbi decoder, the survivor memory unit (SMU) is the most power critical due to data exchanging. A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. The dynamic power of SMU is reduced by the sharing technique. Moreover, the smaller clock loading also leads to power-efficient characteristic. Based on UMC 90nm process, the simulation results show the proposed Viterbi decoder with sharing technique could achieve better power scheme with energy efficiency 0.128 nJ/bit at 0.9V.