TY - GEN
T1 - A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications
AU - Chen, Wei-Zen
AU - Huang, Guan Sheng
PY - 2006/12/1
Y1 - 2006/12/1
N2 - This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is capable of producing 27-1, 210-1, 215-1, 223-1, and 231-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 psrms, and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18μm CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87mW.
AB - This paper presents the design of a low power programmable PRBS generator and a low noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is capable of producing 27-1, 210-1, 215-1, 223-1, and 231-1 b test pattern according to ITU-T recommendations. High speed and low power operations of the PRBS generator are achieved by 16 paths parallel feedback techniques. The measured jitter of the CMU is only 3.56 psrms, and the data jitter at the PRBS output is mainly determined by the CMU. Implemented in a 0.18μm CMOS process, the power dissipation for PRBS generator is only 10.8 mW, and the CMU consumes about 87mW.
UR - http://www.scopus.com/inward/record.url?scp=34547364627&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2006.1693324
DO - 10.1109/ISCAS.2006.1693324
M3 - Conference contribution
AN - SCOPUS:34547364627
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 3273
EP - 3276
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -