A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding

Keyphrases

• Low Power 100%
• Proposed Design 100%
• MPEG-I 100%
• Video Decoding 100%
• Motion Compensation 100%
• Core Design 100%
• IP Core 100%
• Power Consumption 50%
• CMOS Technology 25%
• Design Techniques 25%
• MPEG-4 25%
• Multimedia 25%
• Hardware Complexity 25%
• Video Decoder 25%
• Low-power Design 25%
• System Verification 25%
• Real-time Processing 25%
• Data Sharing 25%
• Xilinx 25%
• Image Interpolation 25%
• Interpolation Process 25%
• FPGA Board 25%
• Cost Consideration 25%

Computer Science

• MPEG 100%
• Motion Compensation 100%
• Power Consumption 50%
• Design Technique 25%
• Multimedia 25%
• Low-Power Design 25%
• Verification System 25%
• Data Sharing 25%
• Time Processing 25%
• Field Programmable Gate Arrays 25%
• Computer Hardware 25%

Engineering

• MPEG 100%
• Intellectual Property Core 100%
• Motion Compensation 100%
• Electric Power Utilization 50%
• Field Programmable Gate Arrays 25%
• Adders 25%
• Design Technique 25%
• Hardware Complexity 25%