TY - JOUR
T1 - A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding
AU - Chih-Da, Chien
AU - Ho-Chun, Chen
AU - Lin-Chieh, Huang
AU - Guo, Jiun-In
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper presents a low-power motion compensation IP core design for the MPEG-1/2/4 video decoding. The proposed design exploits the adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87 % hardware complexity as compared to the quarter-pixel filter in the existing design [4]. In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on the pixel interpolation. After applying the DPGC, we can reduce the 60% power consumption of interpolation operations in the proposed design. Using a 0.18μm CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through XILINX multimedia FPGA board.
AB - This paper presents a low-power motion compensation IP core design for the MPEG-1/2/4 video decoding. The proposed design exploits the adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87 % hardware complexity as compared to the quarter-pixel filter in the existing design [4]. In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on the pixel interpolation. After applying the DPGC, we can reduce the 60% power consumption of interpolation operations in the proposed design. Using a 0.18μm CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through XILINX multimedia FPGA board.
UR - http://www.scopus.com/inward/record.url?scp=67649090474&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465642
DO - 10.1109/ISCAS.2005.1465642
M3 - Conference article
AN - SCOPUS:67649090474
SN - 0271-4310
SP - 4542
EP - 4545
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1465642
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -