A low power configurable SoC for simulating delay-based audio effects

The rapid growth in the capability of modern FPGA devices allows developers to build a complete system on a single chip. These types of FPGA-based SoC (System-On-a-Chip) can normally achieve reduced system power, cost and size, and at the same time offer users a great deal of flexibility. The development of such SoCs normally starts from using a hardware/software co-design methodology in order to partition system tasks into computation-intensive and flexibility-demanding parts. Then, dedicated hardware and software will be implemented to realize these two parts. This paper presents an example which demonstrates the result of applying the hardware/software co-design methodology, a power efficient and performance reliable system architecture for realizing audio delay effects. Compared to similar implementations, our system architecture can save 40% of dynamic power consumption while offering the same data throughput and user flexibility.