A low power configurable SoC for simulating delay-based audio effects

Ling Liu*, Jeremia Bar, Felix Friedrich, Jurg Gutknecht, Shiao-Li Tsao

*此作品的通信作者

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

The rapid growth in the capability of modern FPGA devices allows developers to build a complete system on a single chip. These types of FPGA-based SoC (System-On-a-Chip) can normally achieve reduced system power, cost and size, and at the same time offer users a great deal of flexibility. The development of such SoCs normally starts from using a hardware/software co-design methodology in order to partition system tasks into computation-intensive and flexibility-demanding parts. Then, dedicated hardware and software will be implemented to realize these two parts. This paper presents an example which demonstrates the result of applying the hardware/software co-design methodology, a power efficient and performance reliable system architecture for realizing audio delay effects. Compared to similar implementations, our system architecture can save 40% of dynamic power consumption while offering the same data throughput and user flexibility.

原文English
主出版物標題2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012
DOIs
出版狀態Published - 2012
事件2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012 - Cancun, Mexico
持續時間: 5 12月 20127 12月 2012

出版系列

名字2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012

Conference

Conference2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012
國家/地區Mexico
城市Cancun
期間5/12/127/12/12

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