A low power and high speed Viterbi decoder chip for WLAN applications

Chien Ching Lin, Chia Cho Wu, Chen-Yi Lee

    研究成果: Conference article同行評審

    12 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decision Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power consumption. A test chip is fabricated in 0.35μm IP4M CMOS process, and can achieve the maximum throughput rate of 166Mbit/s under 3.3V. The measured power consumption is below 55mW under 166Mb/s throughput rate at 2.2V.

    原文English
    文章編號1257237
    頁(從 - 到)723-726
    頁數4
    期刊European Solid-State Circuits Conference
    DOIs
    出版狀態Published - 2003
    事件29th European Solid-State Circuits Conference, ESSCIRC 2003 - Estoril, Portugal
    持續時間: 16 9月 200318 9月 2003

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