A Low-Latency Data Compressor for SPAD-Based Depth Estimation Systems

Single-photon avalanche diodes (SPADs)-based depth imagers are vital components of direct time-of-flight (d-ToF) systems, known for their precision and high throughput. With growing demands for improved sensor temporal resolution and extended range, the chip’s output bandwidth becomes a bottleneck for the effective event rate of incoming photons due to the substantial increase in data volume. While conventional data compression techniques can enhance the event rate, they often introduce increased latency from photon-in to data-out. This brief introduces an on-chip data processor designed to prioritize low latency for continuous photon detection. It is characterized by a small photon cluster size and efficient computational and memory utilization. The processor utilizes a two-stage approach that combines delta encoding and entropy compression techniques. Our simulation results demonstrate a data compression ratio of up to 2.33, enabling efficient handling of up to 125 million 12-bit photon events per second within a one-gigabit output bandwidth. We validate the hardware resources requirement using a test chip featuring a 1 × 64 sensor array fabricated in 180 nm technology. This solution is well-prepared to meet the demands of high-speed Light Detection and Ranging (LiDAR) systems.