A low-cost wear-leveling algorithm for block-mapping solid-state disks

Li-Pin Chang*, Li Chun Huang

*此作品的通信作者

研究成果: Conference contribution同行評審

27 引文 斯高帕斯(Scopus)

摘要

Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. However, flash lifetime is becoming a critical issue in the popularity of solidstate disks. Wear-leveling methods can prevent flash-storage devices from prematurely retiring any portions of flash memory. The two practical challenges of wear-leveling design are implementation cost and tuning complexity. This study proposes a new wearleveling design that features both simplicity and adaptiveness. This design requires no new data structures, but utilizes the intelligence available in sector-translating algorithms. Using an on-line tuning method, this design adaptively tunes itself to reach good balance between wear evenness and overhead. A series of trace-driven simulations show that the proposed design outperforms a competitive existing design in terms of wear evenness and overhead reduction. This study also presents a prototype that proves the feasibility of this wear-leveling design in real solid-state disks.

原文English
主出版物標題LCTES'11 - Proceedings of the ACM SIGPLAN/SIGBED 2011 Conference on Languages, Compilers, Tools and Theory for Embedded Systems
頁面31-40
頁數10
DOIs
出版狀態Published - 2011
事件ACM SIGPLAN/SIGBED Conference on Languages Compilers, Tools, and Theory for Embedded Systems, LCTES 2011 - Chicago, IL, 美國
持續時間: 11 4月 201114 4月 2011

出版系列

名字Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Conference

ConferenceACM SIGPLAN/SIGBED Conference on Languages Compilers, Tools, and Theory for Embedded Systems, LCTES 2011
國家/地區美國
城市Chicago, IL
期間11/04/1114/04/11

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