TY - GEN
T1 - A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping Modes
AU - Van, Lan Da
AU - Wang, Yi Ho
AU - Huang, Shen Jui
AU - Chen, Sau Gee
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - In this paper, a low-complexity reconfigurable FFT processor with four data overlapping modes including 75%, 50%, 25%, and nonoverlapping modes (Mode 1, Mode 2, Mode 3, Mode 4, accordingly) is proposed. Utilizing a new merged four N/4-point FFTs algorithm, the transform computation of the overlapped data can be saved and reused. Configuring the proposed three memory banks to store the different N/4 samples and the commutator connections for each mode of an N-point FFT, the reconfigurability can be attained. From the analyses, the proposed FFT can save computation by 55%, 35%, and 15% with N = 1024 compared with the conventional FFT for 75%, 50%, and 25% data overlapping modes, respectively. The proposed work implemented in the TSMC 40nm CMOS process technology shows Mode 1 has the lowest power consumption per FFT by 1.63 mW/FFT.
AB - In this paper, a low-complexity reconfigurable FFT processor with four data overlapping modes including 75%, 50%, 25%, and nonoverlapping modes (Mode 1, Mode 2, Mode 3, Mode 4, accordingly) is proposed. Utilizing a new merged four N/4-point FFTs algorithm, the transform computation of the overlapped data can be saved and reused. Configuring the proposed three memory banks to store the different N/4 samples and the commutator connections for each mode of an N-point FFT, the reconfigurability can be attained. From the analyses, the proposed FFT can save computation by 55%, 35%, and 15% with N = 1024 compared with the conventional FFT for 75%, 50%, and 25% data overlapping modes, respectively. The proposed work implemented in the TSMC 40nm CMOS process technology shows Mode 1 has the lowest power consumption per FFT by 1.63 mW/FFT.
KW - Data overlap
KW - fast Fourier transform
KW - low-complexity
KW - reconfigurable
UR - http://www.scopus.com/inward/record.url?scp=85216130293&partnerID=8YFLogxK
U2 - 10.1109/APCCAS62602.2024.10808748
DO - 10.1109/APCCAS62602.2024.10808748
M3 - Conference contribution
AN - SCOPUS:85216130293
T3 - APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding
SP - 40
EP - 44
BT - APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024
Y2 - 7 November 2024 through 9 November 2024
ER -