A Hybrid Buck Converter Stacked on Auxiliary-switched-capacitor Using Analog and Digital Dynamic Voltage Scaling Techniques

Tzu Ying Wu*, Zeng Shi-Jun, Tz Wun Wang, Sheng Cheng Lee, Ya Ting Hsu, Yu Tse Shih, Jia Rui Huang, Ke Horng Chen, Kuo Lin Zheng, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

The proposed buck stacked auxiliary-switched-capacitor architecture mainly consists of an analog and digital voltage scaling technique to achieve fast dynamic voltage scaling, and an adaptive voltage scaling technique to adapt to chip characteristics. The digital voltage scaling technique can rapidly coarse-tune the output, and the analog voltage scaling technique can fine-tune the output. The up-tracking speed can reach 0.18 μ s/ V and the down-tracking speed can reach 0.13 μ s/ V. The up and down tracking speed can be improved by 4.83X and 7.53X, (a) respectively.

原文English
主出版物標題ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference
發行者IEEE Computer Society
頁面429-432
頁數4
ISBN(電子)9798350304206
DOIs
出版狀態Published - 2023
事件49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal
持續時間: 11 9月 202314 9月 2023

出版系列

名字European Solid-State Circuits Conference
2023-September
ISSN(列印)1930-8833

Conference

Conference49th IEEE European Solid State Circuits Conference, ESSCIRC 2023
國家/地區Portugal
城市Lisbon
期間11/09/2314/09/23

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