A highly efficient vlsi architecture for H.264/AVC level 5.1 CABAC decoder

Yuan Hsin Liao*, Gwo Long Li, Tian-Sheuan Chang

*此作品的通信作者

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)

摘要

In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.

原文English
文章編號5934379
頁(從 - 到)272-281
頁數10
期刊IEEE Transactions on Circuits and Systems for Video Technology
22
發行號2
DOIs
出版狀態Published - 1 二月 2012

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