TY - GEN
T1 - A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture
AU - Chuang, Hsiang Tsung
AU - Tseng, Kai Hsin
AU - Fang, Wai-Chi
PY - 2009/12/1
Y1 - 2009/12/1
N2 - The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm2 on UMC 0.13μm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.
AB - The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm2 on UMC 0.13μm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.
UR - http://www.scopus.com/inward/record.url?scp=77950681408&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2009.5158137
DO - 10.1109/VDAT.2009.5158137
M3 - Conference contribution
AN - SCOPUS:77950681408
SN - 9781424427826
T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
SP - 231
EP - 234
BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Y2 - 28 April 2009 through 30 April 2009
ER -