A high speed Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

Hsie-Chia Chang; Ching Che Chung; Chien Ching Lin; Chen-Yi Lee

A high speed Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

Hsie-Chia Chang, Ching Che Chung, Chien Ching Lin, Chen-Yi Lee

電子研究所

研究成果: Conference article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

In this paper, a high speed Reed-Solomon (RS) decoder chip for optical communications is presented. It mainly contains one (255,239) RS decoder with 4K-bit embedded memory. Due to the operation speed limitation in I/O pad, a Delay Lock Loop (DLL) circuit is also included to generate internal high-speed clock. The RS decoder features a high speed and area-efficient key equation solver using a novel inversionless decomposed architecture for Euclidean algorithm. The test chip is implemented by 0.35μm CMOS SPQM standard cells with chip area of 2.61mm × 2.62mm. The RS decoder has the gate count of 12.4K. Test results show the proposed chip can support 2.35-Gbps data rate while operating at 294MHz with the supply voltage of 3.3V.

原文	English
文章編號	1471579
頁（從 - 到）	519-522
頁數	4
期刊	European Solid-State Circuits Conference
出版狀態	Published - 9月 2002
事件	28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, 意大利持續時間: 24 9月 2002 → 26 9月 2002

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引用此

@article{5d21b25032cd4a808814a0096e8c213c,

title = "A high speed Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm",

abstract = "In this paper, a high speed Reed-Solomon (RS) decoder chip for optical communications is presented. It mainly contains one (255,239) RS decoder with 4K-bit embedded memory. Due to the operation speed limitation in I/O pad, a Delay Lock Loop (DLL) circuit is also included to generate internal high-speed clock. The RS decoder features a high speed and area-efficient key equation solver using a novel inversionless decomposed architecture for Euclidean algorithm. The test chip is implemented by 0.35μm CMOS SPQM standard cells with chip area of 2.61mm × 2.62mm. The RS decoder has the gate count of 12.4K. Test results show the proposed chip can support 2.35-Gbps data rate while operating at 294MHz with the supply voltage of 3.3V.",

author = "Hsie-Chia Chang and Chung, {Ching Che} and Lin, {Chien Ching} and Chen-Yi Lee",

year = "2002",

month = sep,

language = "English",

pages = "519--522",

journal = "European Solid-State Circuits Conference",

issn = "1930-8833",

publisher = "IEEE Computer Society",

note = "28th European Solid-State Circuits Conference, ESSCIRC 2002 ; Conference date: 24-09-2002 Through 26-09-2002",

}

TY - JOUR

T1 - A high speed Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

AU - Chang, Hsie-Chia

AU - Chung, Ching Che

AU - Lin, Chien Ching

AU - Lee, Chen-Yi

PY - 2002/9

Y1 - 2002/9

N2 - In this paper, a high speed Reed-Solomon (RS) decoder chip for optical communications is presented. It mainly contains one (255,239) RS decoder with 4K-bit embedded memory. Due to the operation speed limitation in I/O pad, a Delay Lock Loop (DLL) circuit is also included to generate internal high-speed clock. The RS decoder features a high speed and area-efficient key equation solver using a novel inversionless decomposed architecture for Euclidean algorithm. The test chip is implemented by 0.35μm CMOS SPQM standard cells with chip area of 2.61mm × 2.62mm. The RS decoder has the gate count of 12.4K. Test results show the proposed chip can support 2.35-Gbps data rate while operating at 294MHz with the supply voltage of 3.3V.

AB - In this paper, a high speed Reed-Solomon (RS) decoder chip for optical communications is presented. It mainly contains one (255,239) RS decoder with 4K-bit embedded memory. Due to the operation speed limitation in I/O pad, a Delay Lock Loop (DLL) circuit is also included to generate internal high-speed clock. The RS decoder features a high speed and area-efficient key equation solver using a novel inversionless decomposed architecture for Euclidean algorithm. The test chip is implemented by 0.35μm CMOS SPQM standard cells with chip area of 2.61mm × 2.62mm. The RS decoder has the gate count of 12.4K. Test results show the proposed chip can support 2.35-Gbps data rate while operating at 294MHz with the supply voltage of 3.3V.

UR - http://www.scopus.com/inward/record.url?scp=50149092780&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:50149092780

SN - 1930-8833

SP - 519

EP - 522

JO - European Solid-State Circuits Conference

JF - European Solid-State Circuits Conference

M1 - 1471579

T2 - 28th European Solid-State Circuits Conference, ESSCIRC 2002

Y2 - 24 September 2002 through 26 September 2002

ER -

A high speed Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

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