A High-Speed, Low-Power Divide-By-4 Frequency Divider Implemented with AlInAs/GaInAs HBT’s

C. W. Farley, K. C. Wang, Mau-Chung Chang, Peter M. Asbeck, R. B. Nubling, N. H. Sheng, R. Pierson, G. J. Sullivan

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28 引文 斯高帕斯(Scopus)

摘要

This paper describes the first frequency divider demonstrated using AlInAs/GaInAs heterojunction bipolar transistors (HBT’s). The divider (a static 1/4 divider circuit) operates up to a maximum frequency of 17.1 GHz (corresponding to a gate delay of 29 ps for a bilevel current mode logic (CML) gate with a fan-out of 2) and a total power consumption of 67 mW (about 4.5 mW per equivalent NOR gate). These results demonstrate the potential of AlInAs/GaInAs HBT’s to enable low-power, high-speed integrated circuits.

原文English
頁(從 - 到)377-379
頁數3
期刊IEEE Electron Device Letters
10
發行號8
DOIs
出版狀態Published - 1 一月 1989

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