A high-performance low V MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

Hao I. Yang; Shih Chi Yang; Mao Chih Hsia; Yung Wei Lin; Yi Wei Lin; Chien Hen Chen; Chi Shin Chang; Geng Cing Lin; Yin Nien Chen; Ching Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan Chun Lien; Hung Yu Li; Kuen Di Lee; Wei Chiang Shih; Ya Ping Wu; Wen Ta Lee; Chih Chiang Hsu

doi:10.1109/SOCC.2011.6085080

A high-performance low V _MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

Hao I. Yang^*, Shih Chi Yang, Mao Chih Hsia, Yung Wei Lin, Yi Wei Lin, Chien Hen Chen, Chi Shin Chang, Geng Cing Lin, Yin Nien Chen, Ching Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan Chun Lien, Hung Yu Li, Kuen Di Lee, Wei Chiang Shih, Ya Ping Wu, Wen Ta Lee, Chih Chiang Hsu

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

7 引文斯高帕斯（Scopus）

摘要

This paper describes a high-performance low V _MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V _MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.

原文	English
主出版物標題	Proceedings - IEEE International SOC Conference, SOCC 2011
頁面	197-200
頁數	4
DOIs	https://doi.org/10.1109/SOCC.2011.6085080
出版狀態	Published - 28 12月 2011
事件	24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, 台灣持續時間: 26 9月 2011 → 28 9月 2011

出版系列

名字	International System on Chip Conference
ISSN（列印）	2164-1676
ISSN（電子）	2164-1706

Conference

Conference	24th IEEE International System on Chip Conference, SOCC 2011
國家/地區	台灣
城市	Taipei
期間	26/09/11 → 28/09/11

存取文件

10.1109/SOCC.2011.6085080

其它文件與鏈接

Link to publication in Scopus

引用此

Yang, H. I., Yang, S. C., Hsia, M. C., Lin, Y. W., Lin, Y. W., Chen, C. H., Chang, C. S., Lin, G. C., Chen, Y. N., Chuang, C. T., Hwang, W., Jou, S.-J., Lien, N. C., Li, H. Y., Lee, K. D., Shih, W. C., Wu, Y. P., Lee, W. T., & Hsu, C. C. (2011). A high-performance low V _MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. 於 Proceedings - IEEE International SOC Conference, SOCC 2011 (頁 197-200). 文章 6085080 (International System on Chip Conference). https://doi.org/10.1109/SOCC.2011.6085080

@inproceedings{692bb75e6393464cbbffa63bdcc10282,

title = "A high-performance low V MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control",

abstract = "This paper describes a high-performance low V MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.",

author = "Yang, {Hao I.} and Yang, {Shih Chi} and Hsia, {Mao Chih} and Lin, {Yung Wei} and Lin, {Yi Wei} and Chen, {Chien Hen} and Chang, {Chi Shin} and Lin, {Geng Cing} and Chen, {Yin Nien} and Chuang, {Ching Te} and Wei Hwang and Shyh-Jye Jou and Lien, {Nan Chun} and Li, {Hung Yu} and Lee, {Kuen Di} and Shih, {Wei Chiang} and Wu, {Ya Ping} and Lee, {Wen Ta} and Hsu, {Chih Chiang}",

year = "2011",

month = dec,

day = "28",

doi = "10.1109/SOCC.2011.6085080",

language = "English",

isbn = "9781457716164",

series = "International System on Chip Conference",

pages = "197--200",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2011",

note = "24th IEEE International System on Chip Conference, SOCC 2011 ; Conference date: 26-09-2011 Through 28-09-2011",

}

Yang, HI, Yang, SC, Hsia, MC, Lin, YW, Lin, YW, Chen, CH, Chang, CS, Lin, GC, Chen, YN, Chuang, CT, Hwang, W, Jou, S-J, Lien, NC, Li, HY, Lee, KD, Shih, WC, Wu, YP, Lee, WT & Hsu, CC 2011, A high-performance low V _MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. 於 Proceedings - IEEE International SOC Conference, SOCC 2011., 6085080, International System on Chip Conference, 頁 197-200, 24th IEEE International System on Chip Conference, SOCC 2011, Taipei, 台灣, 26/09/11. https://doi.org/10.1109/SOCC.2011.6085080

TY - GEN

T1 - A high-performance low V MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

AU - Yang, Hao I.

AU - Yang, Shih Chi

AU - Hsia, Mao Chih

AU - Lin, Yung Wei

AU - Lin, Yi Wei

AU - Chen, Chien Hen

AU - Chang, Chi Shin

AU - Lin, Geng Cing

AU - Chen, Yin Nien

AU - Chuang, Ching Te

AU - Hwang, Wei

AU - Jou, Shyh-Jye

AU - Lien, Nan Chun

AU - Li, Hung Yu

AU - Lee, Kuen Di

AU - Shih, Wei Chiang

AU - Wu, Ya Ping

AU - Lee, Wen Ta

AU - Hsu, Chih Chiang

PY - 2011/12/28

Y1 - 2011/12/28

N2 - This paper describes a high-performance low V MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.

AB - This paper describes a high-performance low V MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.

UR - http://www.scopus.com/inward/record.url?scp=84255195488&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2011.6085080

DO - 10.1109/SOCC.2011.6085080

M3 - Conference contribution

AN - SCOPUS:84255195488

SN - 9781457716164

T3 - International System on Chip Conference

SP - 197

EP - 200

BT - Proceedings - IEEE International SOC Conference, SOCC 2011

T2 - 24th IEEE International System on Chip Conference, SOCC 2011

Y2 - 26 September 2011 through 28 September 2011

ER -