A Hardwired Priority-Queue Scheduler for a Four-Core Java SoC

Chun-Jen Tsai, Yan Hung Lin

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents the design and implementation of a hardwired thread scheduler circuit with multi-level priority queues for a four-core Java application processor. A hardwired thread scheduler is much more efficient than the software thread scheduler in a software OS kernel, such as Linux. Since the hardware scheduler can operate in parallel with the processor cores, complex scheduling decisions can be made while the processor cores are running applications. In addition, single-cycle context-switching is possible and no processor core has to waste time running the scheduler. Full-system implementation of a four-core Java processor with the hardware scheduler has been verified using a Xilinx Kintex-7 FPGA device. Performance evaluations show that the proposed system scales up very well and is promising for deeply-embedded multi-thread applications such as the automatic driver assistance systems or the drones.

原文American English
主出版物標題2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538648810
DOIs
出版狀態Published - 26 4月 2018
事件2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
持續時間: 27 5月 201830 5月 2018

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2018-May
ISSN(列印)0271-4310

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
國家/地區Italy
城市Florence
期間27/05/1830/05/18

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