@inproceedings{b05585e8d6f942b4a2ab6d11e825f5fb,
title = "A Hardwired Priority-Queue Scheduler for a Four-Core Java SoC",
abstract = "This paper presents the design and implementation of a hardwired thread scheduler circuit with multi-level priority queues for a four-core Java application processor. A hardwired thread scheduler is much more efficient than the software thread scheduler in a software OS kernel, such as Linux. Since the hardware scheduler can operate in parallel with the processor cores, complex scheduling decisions can be made while the processor cores are running applications. In addition, single-cycle context-switching is possible and no processor core has to waste time running the scheduler. Full-system implementation of a four-core Java processor with the hardware scheduler has been verified using a Xilinx Kintex-7 FPGA device. Performance evaluations show that the proposed system scales up very well and is promising for deeply-embedded multi-thread applications such as the automatic driver assistance systems or the drones.",
keywords = "embedded computing, hardwired OS kernel, multi-core processor, multi-level priority-queue scheduler, SoC",
author = "Chun-Jen Tsai and Lin, {Yan Hung}",
year = "2018",
month = apr,
day = "26",
doi = "10.1109/ISCAS.2018.8351129",
language = "American English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",
address = "United States",
note = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",
}