A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

Chiu Kuo Chen; Ericson Chua; Chih Chung Fu; Shao Yen Tseng; Wai-Chi  Fang

doi:10.1109/ICCE.2011.5722766

A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

Chiu Kuo Chen^*, Ericson Chua, Chih Chung Fu, Shao Yen Tseng, Wai-Chi Fang

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

8 引文斯高帕斯（Scopus）

摘要

This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

原文	English
主出版物標題	2011 IEEE International Conference on Consumer Electronics, ICCE 2011
頁面	607-608
頁數	2
DOIs	https://doi.org/10.1109/ICCE.2011.5722766
出版狀態	Published - 28 3月 2011
事件	2011 IEEE International Conference on Consumer Electronics, ICCE 2011 - Las Vegas, NV, 美國持續時間: 9 1月 2011 → 12 1月 2011

出版系列

名字	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN（列印）	0747-668X

Conference

Conference	2011 IEEE International Conference on Consumer Electronics, ICCE 2011
國家/地區	美國
城市	Las Vegas, NV
期間	9/01/11 → 12/01/11

存取文件

10.1109/ICCE.2011.5722766

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Link to publication in Scopus

引用此

Chen, C. K., Chua, E., Fu, C. C., Tseng, S. Y., & Fang, W.-C. (2011). A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement. 於 2011 IEEE International Conference on Consumer Electronics, ICCE 2011 (頁 607-608). 文章 5722766 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ICCE.2011.5722766

@inproceedings{4e298f9988384c5786a59ef5fab084ef,

title = "A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement",

abstract = "This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.",

author = "Chen, {Chiu Kuo} and Ericson Chua and Fu, {Chih Chung} and Tseng, {Shao Yen} and Wai-Chi Fang",

year = "2011",

month = mar,

day = "28",

doi = "10.1109/ICCE.2011.5722766",

language = "English",

isbn = "9781424487127",

series = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

pages = "607--608",

booktitle = "2011 IEEE International Conference on Consumer Electronics, ICCE 2011",

note = "2011 IEEE International Conference on Consumer Electronics, ICCE 2011 ; Conference date: 09-01-2011 Through 12-01-2011",

}

Chen, CK, Chua, E, Fu, CC, Tseng, SY & Fang, W-C 2011, A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement. 於 2011 IEEE International Conference on Consumer Electronics, ICCE 2011., 5722766, Digest of Technical Papers - IEEE International Conference on Consumer Electronics, 頁 607-608, 2011 IEEE International Conference on Consumer Electronics, ICCE 2011, Las Vegas, NV, 美國, 9/01/11. https://doi.org/10.1109/ICCE.2011.5722766

A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement. / Chen, Chiu Kuo; Chua, Ericson; Fu, Chih Chung 等.
2011 IEEE International Conference on Consumer Electronics, ICCE 2011. 2011. p. 607-608 5722766 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

AU - Chen, Chiu Kuo

AU - Chua, Ericson

AU - Fu, Chih Chung

AU - Tseng, Shao Yen

AU - Fang, Wai-Chi

PY - 2011/3/28

Y1 - 2011/3/28

N2 - This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

AB - This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=79952955656&partnerID=8YFLogxK

U2 - 10.1109/ICCE.2011.5722766

DO - 10.1109/ICCE.2011.5722766

M3 - Conference contribution

AN - SCOPUS:79952955656

SN - 9781424487127

T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

SP - 607

EP - 608

BT - 2011 IEEE International Conference on Consumer Electronics, ICCE 2011

T2 - 2011 IEEE International Conference on Consumer Electronics, ICCE 2011

Y2 - 9 January 2011 through 12 January 2011

ER -

A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

摘要

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Conference

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