摘要
This letter proposes a fully integrated step-down switched-capacitor (SC) DC-DC converter using 0.18-mu m CMOS technology for system-on-chip applications. The proposed stepdown switched-capacitor DC-DC converter used two control mechanisms: the switch array modulation technique to regulate the output voltage and the voltage ripple modulation technique to adjust the output voltage ripple of the converter as the loading current varied. As a result, the proposed converter could generate a regulated output voltage with low voltage ripple. The converter core performed at conversion ratios of 1/3 and 1/2 under an input voltage of 1.8 V. The measurement results on 180-nm technology showed that the proposed fully integrated step-down switched-capacitor DC-DC converter could achieve a peak power conversion efficiency of 74.1% and maintain power conversion efficiency at levels over 70% within loading ranges between 1.4 and 5 mA. The output voltage ripple was controlled at levels under 63.4 mV within a loading current ranging between 0.1 and 5 mA.
| 原文 | English |
|---|---|
| 頁（從 - 到） | 1649-1653 |
| 頁數 | 5 |
| 期刊 | IEEE Transactions on Circuits and Systems I: Regular Papers |
| 卷 | 67 |
| 發行號 | 9 |
| DOIs | |
| 出版狀態 | Published - 9月 2020 |
| 事件 | 3rd International Symposium on Integrated Circuits and Systems (ISICAS) - 持續時間: 27 8月 2020 → 28 8月 2020 |