A fully-integrated low-power 2.4-GHZ CMOS transceiver for wireless personal area network applications

Chia Pei Chen*, Kuei-Ann Wen, Ming Jen Yang, Hsun Hsiu Huang, Tung Ying Chiang, Jheng Liang Chen, Ming Chieh Chen, Hong Sing Kao, Chung Chih Su, Fong Wei Kuo

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    研究成果: Article同行評審

    摘要

    A low-power transceiver consuming 13 mA and 19 mA in the transmit and receive mode, respectively, is designed to operate with a minimum supply voltage of 1.9 V. The receiver employs a dual-conversion low-IF architecture to reduce the current consumption efficiently. With the assistance of an outstanding demodulator, it can achieve a sensitivity of-88 dBm at 0.1% BER with 1-Mb/s data rate. The transmitter adopts an architecture of open-loop VCO modulation to save significant power during data transmitting. It delivers a GFSK modulated spectrum with a nominal output power of 0 dBm. The chip was fabricated on a 4-mm 2 die using a 0.18-um CMOS process.

    原文English
    頁(從 - 到)489-499
    頁數11
    期刊International Journal of Electrical Engineering
    15
    發行號6
    出版狀態Published - 1 12月 2008

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