@inproceedings{f4a3a06feeb646978e4c5a72c428ef35,
title = "21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing",
abstract = "Next-generation sequencing (NGS) is now indispensable for genetics research and biomedical applications, such as disease analysis and evolution tracking [1]. However, it still takes up to a couple of days to analyze all genetic mutations (variants) of a human genome, which consists of 3 billion nucleotides, through GPU acceleration. Fig. 21.1.1 shows an overview of NGS and the data analysis workflow. The NGS technology enables sequencing hundreds of millions of DNA segments, anchored and amplified on a microarray, in parallel. In each sequencing cycle, the nucleotides (A, T, C, G) are individually detected by their unique fluorescence labels and DNA segments can then be constructed as short reads. The NGS data analysis workflow consists of Preprocessing, Short-Read Mapping (including Exact Matching and Inexact Matching), Haplotype Calling, and Variant Calling [2]. Short reads are first mapped to a reference DNA and further used to assemble the genome of the DNA sample. Preprocessing is essential for constructing the data structure for indexing the reference DNA. In Short-Read Mapping, a seeding-and-extension scheme is applied to perform both Exact and Inexact Matching. The equal-length sub-sequences (seeds) of the short reads are used to find the exact locations on the reference DNA. Then, the seeds are extended to identify the most-likely locations through global alignment, allowing mismatches and insertions/deletions [2]. Next, in Haplotype Calling, the reads mapped to a specific region are assembled to reconstruct the paternal and maternal genomes (i.e. haplotypes) of the DNA sample. Finally, in Variant Calling, the assembled haplotypes are used to determine the variants between the reference DNA and the sample DNA. The outputs of Variant Calling indicate the location and likelihood of each variant. Dedicated VLSI solutions have been developed for acceleration, but only Suffix-Array (SA) Sorting for Preprocessing and Exact Matching for Short-Read Mapping were realized on silicon [3]. This work presents a fully integrated SoC for the entire NGS data analysis process.",
author = "Wu, {Yi Chung} and Chen, {Yen Lung} and Yang, {Chung Hsuan} and Lee, {Chao Hsi} and Yu, {Chao Yang} and Chang, {Nian Shyang} and Chen, {Ling Chien} and Chang, {Jia Rong} and Lin, {Chun Pin} and Chen, {Hung Lieh} and Chen, {Chi Shi} and Hung, {Jui Hung} and Yang, {Chia Hsiang}",
year = "2020",
month = feb,
doi = "10.1109/ISSCC19947.2020.9063002",
language = "English",
isbn = "978-1-7281-3206-8",
series = "IEEE International Solid State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "322--324",
booktitle = "2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC)",
address = "United States",
note = "2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 ; Conference date: 16-02-2020 Through 20-02-2020",
}