A fourth-order incremental ADC in three-step

This letter presents a second-order incremental ADC (IADC) operated in three steps, which extends the performance of a second-order IADC close to that of a fourth-order IADC with only two amplifiers. It performs a second-order noise-shaping quantization in the first step operation. Reusing the same hardware, the circuit is reconfigured to perform fine quantization as a first-order IADC in the second and third step. Within a conversion time of 60 clock periods (oversampling ratio OSR = 60), 35 dB signal-to-quantization-noise ratio is boosted. The proposed topology is very suitable for low-bandwidth high-resolution data conversion.