A fast settling and low reference spur PLL with double sampling phase detector

Guo Jue Huang; Che Sheng Chen; Wen Slien Wuen; Kuei-Ann Wen

doi:10.1109/ICECS.2008.4674854

A fast settling and low reference spur PLL with double sampling phase detector

Guo Jue Huang^*, Che Sheng Chen, Wen Slien Wuen, Kuei-Ann Wen

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and low reference spur. By comparing the DSPD architecture to the conventional PD architecture, the settling time can be reduced 50% in the 30ppm frequency accuracy and the reference spur can be suppressed 5.9 dB.

原文	English
主出版物標題	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
頁面	316-319
頁數	4
DOIs	https://doi.org/10.1109/ICECS.2008.4674854
出版狀態	Published - 26 12月 2008
事件	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta 持續時間: 31 8月 2008 → 3 9月 2008

出版系列

名字	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
國家/地區	Malta
城市	St. Julian's
期間	31/08/08 → 3/09/08

存取文件

10.1109/ICECS.2008.4674854

其它文件與鏈接

Link to publication in Scopus

引用此

Huang, G. J., Chen, C. S., Wuen, W. S., & Wen, K-A. (2008). A fast settling and low reference spur PLL with double sampling phase detector. 於 Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (頁 316-319). [4674854] (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4674854

@inproceedings{2c1296b0ae8b42ef9c86db2e264de321,

title = "A fast settling and low reference spur PLL with double sampling phase detector",

abstract = "This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and low reference spur. By comparing the DSPD architecture to the conventional PD architecture, the settling time can be reduced 50% in the 30ppm frequency accuracy and the reference spur can be suppressed 5.9 dB.",

author = "Huang, {Guo Jue} and Chen, {Che Sheng} and Wuen, {Wen Slien} and Kuei-Ann Wen",

year = "2008",

month = dec,

day = "26",

doi = "10.1109/ICECS.2008.4674854",

language = "English",

isbn = "9781424421824",

series = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

pages = "316--319",

booktitle = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

note = "null ; Conference date: 31-08-2008 Through 03-09-2008",

}

Huang, GJ, Chen, CS, Wuen, WS & Wen, K-A 2008, A fast settling and low reference spur PLL with double sampling phase detector. 於 Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4674854, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, 頁 316-319, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, Malta, 31/08/08. https://doi.org/10.1109/ICECS.2008.4674854

A fast settling and low reference spur PLL with double sampling phase detector. / Huang, Guo Jue; Chen, Che Sheng; Wuen, Wen Slien 等.

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 316-319 4674854 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A fast settling and low reference spur PLL with double sampling phase detector

AU - Huang, Guo Jue

AU - Chen, Che Sheng

AU - Wuen, Wen Slien

AU - Wen, Kuei-Ann

PY - 2008/12/26

Y1 - 2008/12/26

N2 - This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and low reference spur. By comparing the DSPD architecture to the conventional PD architecture, the settling time can be reduced 50% in the 30ppm frequency accuracy and the reference spur can be suppressed 5.9 dB.

AB - This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and low reference spur. By comparing the DSPD architecture to the conventional PD architecture, the settling time can be reduced 50% in the 30ppm frequency accuracy and the reference spur can be suppressed 5.9 dB.

UR - http://www.scopus.com/inward/record.url?scp=57849103665&partnerID=8YFLogxK

U2 - 10.1109/ICECS.2008.4674854

DO - 10.1109/ICECS.2008.4674854

M3 - Conference contribution

AN - SCOPUS:57849103665

SN - 9781424421824

T3 - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

SP - 316

EP - 319

BT - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Y2 - 31 August 2008 through 3 September 2008

ER -

Huang GJ, Chen CS, Wuen WS, Wen K-A. A fast settling and low reference spur PLL with double sampling phase detector. 於 Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 316-319. 4674854. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). doi: 10.1109/ICECS.2008.4674854

A fast settling and low reference spur PLL with double sampling phase detector

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此