A fast settling and low reference spur PLL with double sampling phase detector

Guo Jue Huang*, Che Sheng Chen, Wen Slien Wuen, Kuei-Ann Wen

*此作品的通信作者

    研究成果: Conference contribution同行評審

    摘要

    This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and low reference spur. By comparing the DSPD architecture to the conventional PD architecture, the settling time can be reduced 50% in the 30ppm frequency accuracy and the reference spur can be suppressed 5.9 dB.

    原文English
    主出版物標題Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
    頁面316-319
    頁數4
    DOIs
    出版狀態Published - 26 12月 2008
    事件15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
    持續時間: 31 8月 20083 9月 2008

    出版系列

    名字Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

    Conference

    Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
    國家/地區Malta
    城市St. Julian's
    期間31/08/083/09/08

    指紋

    深入研究「A fast settling and low reference spur PLL with double sampling phase detector」主題。共同形成了獨特的指紋。

    引用此