A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator

Hsing Chien Chu, Yi Hsiang Hua, Chung-Chih Hung

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.

原文English
主出版物標題2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面375-378
頁數4
ISBN(電子)9781509018307
DOIs
出版狀態Published - 15 12月 2016
事件2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong
持續時間: 3 8月 20165 8月 2016

出版系列

名字2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016

Conference

Conference2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
國家/地區Hong Kong
城市Hong Kong
期間3/08/165/08/16

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