TY - JOUR
T1 - A Fast 1-D Serial-Parallel Systolic Multiplier
AU - Wu, I-Chen
PY - 1987/1/1
Y1 - 1987/1/1
N2 - Based on the modified Booth's algorithm, a fast 1-D serial-parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n ≤ N) multiplier and an m-bit multiplicand is equal to n + m – 1, and independent of the circuit size N.
AB - Based on the modified Booth's algorithm, a fast 1-D serial-parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n ≤ N) multiplier and an m-bit multiplicand is equal to n + m – 1, and independent of the circuit size N.
KW - Countercurrent data flow pattern
KW - five-level multiplexer
KW - five-level recorder
KW - modified Booth's Algorithm
KW - systolic multiplier
KW - two's complement, VLSI
UR - http://www.scopus.com/inward/record.url?scp=0000292236&partnerID=8YFLogxK
U2 - 10.1109/TC.1987.1676865
DO - 10.1109/TC.1987.1676865
M3 - Article
AN - SCOPUS:0000292236
SN - 0018-9340
VL - C-36
SP - 1243
EP - 1247
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
IS - 10
ER -