A dual-level dual-phase pulse-width modulation class-D amplifier with 0.001% THD, 112 dB SNR

Shang Hsien Yang, Yuan Han Yang, Ke-Horng Chen, Chung-Chih Hung, Chin Long Wey, Ying Hsi Lin, Tsung Yen Tsai, Chen Chih Huang, Chao Cheng Lee, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin Yu Luo, Shih Ming Wang, Long Der Chen, Cheng Chen Yang, Huang Tian Hui

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180° out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.

原文English
主出版物標題2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2676-2679
頁數4
ISBN(列印)9781479934324
DOIs
出版狀態Published - 2014
事件2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
持續時間: 1 6月 20145 6月 2014

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家/地區Australia
城市Melbourne, VIC
期間1/06/145/06/14

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