TY - GEN
T1 - A dual-band four-mode δ-Σ frequency synthesizer
AU - Chen, Wei-Zen
AU - Yu, Dai An
PY - 2006
Y1 - 2006
N2 - This paper describes the design of a dual-band, four-mode Δ-Σ frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3rd order Δ-Σ modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 μ sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-μm CMOS process, the chip size is 1.95 mm2. The total power consumption is 19.54 mW from a 1.8 V power supply.
AB - This paper describes the design of a dual-band, four-mode Δ-Σ frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3rd order Δ-Σ modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 μ sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-μm CMOS process, the chip size is 1.95 mm2. The total power consumption is 19.54 mW from a 1.8 V power supply.
UR - http://www.scopus.com/inward/record.url?scp=33845892558&partnerID=8YFLogxK
U2 - 10.1109/RFIC.2006.1651125
DO - 10.1109/RFIC.2006.1651125
M3 - Conference contribution
AN - SCOPUS:33845892558
SN - 0780395727
SN - 9780780395725
T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
SP - 197
EP - 200
BT - 2006 IEEE Radio Frequency Integrated Circuits(RFIC) Symposium - Digest of Papers
T2 - 2006 IEEE Radio Frequency Integrated Circuits Symposium
Y2 - 11 June 2006 through 13 June 2006
ER -