A dual-band four-mode δ-Σ frequency synthesizer

Wei-Zen Chen*, Dai An Yu

*此作品的通信作者

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper describes the design of a dual-band, four-mode Δ-Σ frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3rd order Δ-Σ modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 μ sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-μm CMOS process, the chip size is 1.95 mm2. The total power consumption is 19.54 mW from a 1.8 V power supply.

原文English
主出版物標題2006 IEEE Radio Frequency Integrated Circuits(RFIC) Symposium - Digest of Papers
頁面197-200
頁數4
DOIs
出版狀態Published - 1 十二月 2006
事件2006 IEEE Radio Frequency Integrated Circuits Symposium - San Francisco, CA, United States
持續時間: 11 六月 200613 六月 2006

出版系列

名字Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
2006
ISSN(列印)1529-2517

Conference

Conference2006 IEEE Radio Frequency Integrated Circuits Symposium
國家/地區United States
城市San Francisco, CA
期間11/06/0613/06/06

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