A double-issue Java processor design for embedded applications

Hou J. Ko*, Chun-Jen Tsai

*此作品的通信作者

研究成果: Conference article同行評審

7 引文 斯高帕斯(Scopus)

摘要

Java applications for embedded systems are becoming popular today. CLDC/MIDP is the standard application platform for mobile phones while CDC/PBP is the emerging application platform for next generation digital TV set-top boxes. Although software-based Java Virtual Machines (VM) are prevalent, most of these VMs require a host processor running at much higher clock rate than 300MHz to reach reasonable performance. This is beyond the recommended specification of handsets and set-top boxes. In this paper, we have proposed a double-issue java processor for embedded systems. The design is not tied to any host processors and can be used as an efficient binary execution engine for a full Java Runtime Environment implementation. When synthesized on a Virtex IV FPGA (4VFX12FF66-10), the RTL model can reach over 100MHz and consumes less than 22% resources of the device.

原文English
文章編號4253435
頁(從 - 到)3502-3505
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 2007
事件2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
持續時間: 27 5月 200730 5月 2007

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