A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs

Shea Smith, Armin Tajalli, Yen Cheng Kuan, Shiuh hua Wood Chiang

研究成果: Article同行評審

摘要

VCO-based ADCs widely utilize coarse-fine readout to save power and hardware compared to counter-only converters. However, the timing mismatch due to the clock skew between the coarse and fine quantizers can lead to significant reconstruction errors. This paper proposes a digital calibration circuit to detect and correct coarse-fine timing mismatch for VCO-based ADCs. The circuit includes overcount/undercount logic to detect all possible timing mismatch cases and generates a correction value to digitally remove the errors. The calibration operates continuously in the background and is entirely digital, making it scaling-friendly and robust against analog imperfections. Simulations show that a VCO-based ADC utilizing the calibration circuit improves the SNR by 10.3 dB and 6.9 dB versus a conventional coarse-fine converter and one with a conventional retiming calibration, respectively.

原文English
頁(從 - 到)1
頁數1
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
出版狀態Accepted/In press - 2024

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