A design-for-verification technique for functional pattern reduction

Chien-Nan Liu; I. Ling Chen; Jing Yang Jou

doi:10.1109/MDT.2003.1188262

A design-for-verification technique for functional pattern reduction

Chien-Nan Liu, I. Ling Chen, Jing Yang Jou^*

^*此作品的通信作者

電子研究所

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A design-for-verification (DFV) technique for functional pattern reduction was discussed. It was suggested that applying similar ideas to functional verification could enable an increase in simulation coverage and reduce verification time by the insertion of some DFV points into hardware description level (HDL) designs. The results showed that the number of hard-to-control (HTC) register nodes and the number of selected nodes were not always the same.

原文	English
頁（從 - 到）	48-55
頁數	8
期刊	IEEE Design and Test of Computers
卷	20
發行號	2
DOIs	https://doi.org/10.1109/MDT.2003.1188262
出版狀態	Published - 1 3月 2003

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10.1109/MDT.2003.1188262

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A design-for-verification technique for functional pattern reduction

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