A design-for-verification technique for debugging HDL designs

Chien-Nan Liu*


研究成果: Article同行評審


Recently, verification has become the major bottleneck of the entire design process for complex circuits. Similar to the well-known "design-for- testability" techniques, "design-for-verification" (DFV) techniques were proposed for functional verification to help users reduce the verification efforts. The previous DFV techniques can help users reduce the number of input patterns for verification but cannot help users locate the error sources. Therefore, in this paper, we propose another DFV technique to help users reduce their efforts on debugging their designs. With the help of the proposed algorithms, we can set up several comparison points to reduce the size of searching space in the debugging process. The simulation overhead can also be controlled because we only set up comparison points on necessary registers, not all of them.

頁(從 - 到)99-104
期刊International Journal of Electrical Engineering
出版狀態Published - 2月 2005


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