A design flow for multiplierless linear-phase fir filters: From system specification to verilog code

Kai Yuan Jheng*, Shyh-Jye Jou, An Y. Wu

*此作品的通信作者

    研究成果: Conference article同行評審

    21 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.

    原文English
    頁(從 - 到)V-293-V-296
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    5
    DOIs
    出版狀態Published - 2004
    事件2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
    持續時間: 23 5月 200426 5月 2004

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