A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design

Ming Yu Huang, Hung-Ming Chen, Kuan-Neng Chen, Shih Hsien Wu, Yu-Min Lee, An Yu Su

研究成果: Conference contribution同行評審

摘要

Micro bumps and stripes play essential roles for the transmission of signals and the preservation of power integrity in the modern flip-chip packaging process. For different placement block designs on a chip, the best micro bump arrangement and stripe generation method is usually varied accordingly. It often takes a lot of manpower and time cost in generating the delivery path of signal and power transmission in a package. As a result, we propose a way that can automatically generate a power delivery network (PDN) on the top metal layers in a chip and set the coordinate of micro bumps. It can solve the IR drop problem in the early stage, and decrease the integrated circuit (IC) and packaging layout design iteration, thus shorten time-to-market (TTM). Experimental results show that our flows can reduce IR drop to 5% of supply voltage in block.

原文English
主出版物標題Proceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2236-2241
頁數6
ISBN(電子)9781728161808
ISBN(列印)978-1-7281-6181-5
DOIs
出版狀態Published - 六月 2020
事件70th IEEE Electronic Components and Technology Conference, ECTC 2020 - Orlando, United States
持續時間: 3 六月 202030 六月 2020

出版系列

名字Proceedings - Electronic Components and Technology Conference
2020-June
ISSN(列印)0569-5503

Conference

Conference70th IEEE Electronic Components and Technology Conference, ECTC 2020
國家/地區United States
城市Orlando
期間3/06/2030/06/20

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