A DC-to-18 GHz 6-bit CMOS Digital Step Attenuator with Low Phase Error and Compact Size

Jianbin Liu, Tao Yang, Pei Ling Chi

研究成果: Conference contribution同行評審

摘要

In this paper, a DC-to-18 GHz low phase error 6-bit digitally controlled attenuator fabricated in CMOS 55nm process is proposed. The proposed attenuator utilizes a phase-compensated structure to minimize the phase difference between the reference state and the attenuation state, resulting in a low root mean square (RMS) phase error. Additionally, the cascading method of the attenuation units is optimized to ensure accurate attenuation across a wide range. Experimental measurements demonstrate that the designed digital attenuator achieves a maximum RMS phase error of less than 4° within the operating frequency band. It offers an attenuation range of 31.5 dB with a step size of 0.5 dB. Remarkably, the core area, excluding the pad, occupies a small area of 0.015

原文English
主出版物標題7th International Symposium on Electromagnetic Compatibility, ISEMC 2023 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350333107
DOIs
出版狀態Published - 2023
事件7th IEEE International Symposium on Electromagnetic Compatibility, ISEMC 2023 - Hangzhou, 中國
持續時間: 20 10月 202323 10月 2023

出版系列

名字IEEE International Symposium on Electromagnetic Compatibility
ISSN(列印)1077-4076
ISSN(電子)2158-1118

Conference

Conference7th IEEE International Symposium on Electromagnetic Compatibility, ISEMC 2023
國家/地區中國
城市Hangzhou
期間20/10/2323/10/23

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