A cost-effective reconfigurable accelerator for platform-based SoC design

Lan-Da Van*, Hsin Fu Luo, Nien Hsiang Chang, Chun Ming Huang

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigurable computation array (RCA) can be landed with the features of high usage rate and low hardware cost without sacrificing multimedia computation performance. The RCA consisting of 8 type 1 grouped processing elements (GPE1's), 3 GPE2's and 1 GPE3 is capable of configuring two 16×16-bit multiplication, eight 8×8 multiplication, and sixteen 8-bit absolute operations in different connection topologies. Via the cost-effective RCA, the number of GPEs can be saved up to 25% and the usage rates of the RCA compared with that of [8] for motion estimation (ME), RGB2YUV and DCT/IDCT can be improved by 25%, 18.7%, and 23.9%, respectively.

原文English
主出版物標題ISCAS 2006
主出版物子標題2006 IEEE International Symposium on Circuits and Systems, Proceedings
頁面1977-1980
頁數4
DOIs
出版狀態Published - 1 12月 2006
事件ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, 希臘
持續時間: 21 5月 200624 5月 2006

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
國家/地區希臘
城市Kos
期間21/05/0624/05/06

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