A Controlled-Avalanche Superlattice Transistor

Pallab K. Bhattacharya; Albert Chin; Kwang S. Seo

doi:10.1109/EDL.1987.26536

A Controlled-Avalanche Superlattice Transistor

Pallab K. Bhattacharya, Albert Chin, Kwang S. Seo

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2 引文斯高帕斯（Scopus）

摘要

A novel bipolar avalanche transistor is proposed. Controlled avalanche and large current output over a significant bias region is achieved by incorporating a staircase multiplication region at the base-collector junction. The III-V materials choice, device design, and computed output characteristics are presented and discussed.

原文	English
頁（從 - 到）	19-21
頁數	3
期刊	Ieee Electron Device Letters
卷	8
發行號	1
DOIs	https://doi.org/10.1109/EDL.1987.26536
出版狀態	Published - 1月 1987

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10.1109/EDL.1987.26536

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A Controlled-Avalanche Superlattice Transistor

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