A continuous-time delta-sigma modulator using feedback resistors

Yung Chou Lin*, Wen Hung Hsieh, Chung-Chih Hung

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

A third-order continuous-time delta-sigma comprised of Active- RC integrator and Gm-C integrator is presented. For the consideration of power, linearity and performance, the first integrator uses active-RC OpAmp and the others use Gm-C. To reduce the clock jitter sensitivity, we choose nonreturn-to-zero (NRZ) pulse shaping as our DAC type. For the realization of NTF zero optimization, we use resistors to reduce power consumption. The delta-sigma modulator is implemented in standard digital 0.18-μm CMOS process which achieves a 60-dB SNDR or 10-bits ENOB over a 1-MHz signal bandwidth at an OSR of 50. The power consumption of the continuous-time delta-sigma modulator itself is 13.7 mW from the 1.8-V supply.

原文English
主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
頁面243-246
頁數4
DOIs
出版狀態Published - 2009
事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
持續時間: 28 4月 200930 4月 2009

出版系列

名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
國家/地區Taiwan
城市Hsinchu
期間28/04/0930/04/09

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