A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

Sheng Luo; Kain Lu Low; Xiaoyi Zhang; Qianyu Zhao; Hsin Lin; Gengchiau Liang

doi:10.1109/EDTM.2017.7947510

A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

Sheng Luo^*, Kain Lu Low, Xiaoyi Zhang, Qianyu Zhao, Hsin Lin, Gengchiau Liang

^*此作品的通信作者

前瞻半導體研究所

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS₂-WSe₂ VTFET.

原文	English
主出版物標題	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	70-71
頁數	2
ISBN（電子）	9781509046591
DOIs	https://doi.org/10.1109/EDTM.2017.7947510
出版狀態	Published - 13 6月 2017
事件	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Toyama, 日本持續時間: 28 2月 2017 → 2 3月 2017

出版系列

名字	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings

Conference

Conference	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017
國家/地區	日本
城市	Toyama
期間	28/02/17 → 2/03/17

存取文件

10.1109/EDTM.2017.7947510

其它文件與鏈接

Link to publication in Scopus

引用此

Luo, S., Low, K. L., Zhang, X., Zhao, Q., Lin, H., & Liang, G. (2017). A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. 於 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings (頁 70-71). 文章 7947510 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM.2017.7947510

Luo, Sheng ; Low, Kain Lu ; Zhang, Xiaoyi 等. / A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 頁 70-71 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings).

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title = "A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor",

abstract = "A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS2-WSe2 VTFET.",

author = "Sheng Luo and Low, {Kain Lu} and Xiaoyi Zhang and Qianyu Zhao and Hsin Lin and Gengchiau Liang",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 ; Conference date: 28-02-2017 Through 02-03-2017",

year = "2017",

month = jun,

day = "13",

doi = "10.1109/EDTM.2017.7947510",

language = "English",

series = "2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "70--71",

booktitle = "2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings",

address = "美國",

}

Luo, S, Low, KL, Zhang, X, Zhao, Q, Lin, H & Liang, G 2017, A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. 於 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings., 7947510, 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 頁 70-71, 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017, Toyama, 日本, 28/02/17. https://doi.org/10.1109/EDTM.2017.7947510

A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. / Luo, Sheng; Low, Kain Lu; Zhang, Xiaoyi 等.
2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 70-71 7947510 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

AU - Luo, Sheng

AU - Low, Kain Lu

AU - Zhang, Xiaoyi

AU - Zhao, Qianyu

AU - Lin, Hsin

AU - Liang, Gengchiau

PY - 2017/6/13

Y1 - 2017/6/13

N2 - A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS2-WSe2 VTFET.

AB - A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current and improve subthreshold region performance. A drive current ∼421.6μA/μm is obtained based on the structural-optimized MoS2-WSe2 VTFET.

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U2 - 10.1109/EDTM.2017.7947510

DO - 10.1109/EDTM.2017.7947510

M3 - Conference contribution

AN - SCOPUS:85021899483

T3 - 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings

SP - 70

EP - 71

BT - 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017

Y2 - 28 February 2017 through 2 March 2017

ER -

Luo S, Low KL, Zhang X, Zhao Q, Lin H, Liang G. A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor. 於 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 70-71. 7947510. (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings). doi: 10.1109/EDTM.2017.7947510

A computational study of fundamentals and design considerations for vertical tunneling field-effect transistor

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Conference

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