A comprehensive characterization method for lateral profiling of interface traps and trapped charges in P-SONOS cell devices

Jyh-Chyurn Guo, Pei Ying Du

研究成果: Article同行評審

摘要

A comprehensive characterization method has been developed in this paper for reliable lateral profiling of the interface traps (ΔNit), localized charges (ΔNot), and trapped holes (ΔNhole) in P-SONOS cell devices. Charge pumping current (ICP) measurement can be used to probe ΔNit and ΔNot from the increase of maximum ICP(ICP, max) and the shift of ICP curve along the base level voltage (Vb). When increasing the program and erase (P/E) cycles, the negative threshold voltage (VT) shift at both program and erase states suggests the generation of ΔNhole. The evolution of ΔNit , ΔNot , and ΔNhole during P/E cycling can consistently explain the nonmonotonic variations of gate induced drain leakage current (IGIDL) and substrate current (ISUB) as well as dramatic differences between the source and drain. The lateral migration of ΔNot caused by extending P/E cycles may lead to the failure of two-bit operation in SONOS cell devices. The larger VT shift and subthreshold swing, smaller read current, and lower transconductance may degrade the endurance and retention of P-SONOS when applied in Flash memory.

原文English
文章編號7738415
頁(從 - 到)121-129
頁數9
期刊IEEE Transactions on Device and Materials Reliability
17
發行號1
DOIs
出版狀態Published - 1 3月 2017

指紋

深入研究「A comprehensive characterization method for lateral profiling of interface traps and trapped charges in P-SONOS cell devices」主題。共同形成了獨特的指紋。

引用此