A CMOS distributed amplifier with current reuse optimization

Mei Fen Chou; Wen An Tsou; Robert H. Dunn; Hsiang Lin Huang; Kuei-Ann Wen; Chun Yen Chang

doi:10.1109/ISCAS.2006.1693275

A CMOS distributed amplifier with current reuse optimization

Mei Fen Chou^*, Wen An Tsou, Robert H. Dunn, Hsiang Lin Huang, Kuei-Ann Wen, Chun Yen Chang

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption While retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only 12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-μm CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide-band transceivers.

原文	English
主出版物標題	ISCAS 2006
主出版物子標題	2006 IEEE International Symposium on Circuits and Systems, Proceedings
頁面	3077-3080
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2006.1693275
出版狀態	Published - 1 12月 2006
事件	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece 持續時間: 21 5月 2006 → 24 5月 2006

出版系列

名字	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN（列印）	0271-4310

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
國家/地區	Greece
城市	Kos
期間	21/05/06 → 24/05/06

存取文件

10.1109/ISCAS.2006.1693275

其它文件與鏈接

Link to publication in Scopus

引用此

Chou, M. F., Tsou, W. A., Dunn, R. H., Huang, H. L., Wen, K-A., & Chang, C. Y. (2006). A CMOS distributed amplifier with current reuse optimization. 於 ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (頁 3077-3080). [1693275] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2006.1693275

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title = "A CMOS distributed amplifier with current reuse optimization",

abstract = "A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption While retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only 12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-μm CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide-band transceivers.",

author = "Chou, {Mei Fen} and Tsou, {Wen An} and Dunn, {Robert H.} and Huang, {Hsiang Lin} and Kuei-Ann Wen and Chang, {Chun Yen}",

year = "2006",

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doi = "10.1109/ISCAS.2006.1693275",

language = "English",

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Chou, MF, Tsou, WA, Dunn, RH, Huang, HL, Wen, K-A & Chang, CY 2006, A CMOS distributed amplifier with current reuse optimization. 於 ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693275, Proceedings - IEEE International Symposium on Circuits and Systems, 頁 3077-3080, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06. https://doi.org/10.1109/ISCAS.2006.1693275

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AU - Tsou, Wen An

AU - Dunn, Robert H.

AU - Huang, Hsiang Lin

AU - Wen, Kuei-Ann

AU - Chang, Chun Yen

PY - 2006/12/1

Y1 - 2006/12/1

N2 - A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption While retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only 12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-μm CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide-band transceivers.

AB - A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption While retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only 12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-μm CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide-band transceivers.

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U2 - 10.1109/ISCAS.2006.1693275

DO - 10.1109/ISCAS.2006.1693275

M3 - Conference contribution

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SN - 0780393902

SN - 9780780393905

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - ISCAS 2006

Y2 - 21 May 2006 through 24 May 2006

ER -

A CMOS distributed amplifier with current reuse optimization

摘要

出版系列

Conference

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