A CMOS Buffer Amplifier with Slew-Rate Enhancement and Power Saving Techniques

Liang Jie Lu, Po Hsun Chu, Wei Chen Huang, Yu Te Liao

研究成果: Conference contribution同行評審

摘要

This paper presents a low-power buffer amplifier with a high slew rate. The buffer amplifier with cross-coupled input pairs and positive feedback enhances the driving current at the transients dynamically. The adaptive bias-switching scheme reduces static power consumption. The design was fabricated in a 0.18-μ m CMOS process. The proposed amplifier offers a slew rate of 13.42 V/μ s at a load capacitor of 100 pF with a static current of 2.38 μ A, which is 80 times better than the one without the current-boosting scheme. The chip area is 189× 144 μ m2.

原文English
主出版物標題2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350334166
DOIs
出版狀態Published - 2023
事件2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan
持續時間: 17 4月 202320 4月 2023

出版系列

名字2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
國家/地區Taiwan
城市Hsinchu
期間17/04/2320/04/23

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